The invention relates to electronic memory storage devices and more particularly to electronic memory data access timing to ensure sufficient set up time for output data.
Data memory is a common electronic device used for storage and retrieval of data. Typically, data memory stored data in the form of a pair of potential electronic valuesxe2x80x94on or off; xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d xe2x80x94which are arbitrarily assigned to one of the available electronic states during design or design in.
The first data memory storage devices were space consuming, power consuming, slow circuits implemented based on the conventional flip flop, each flip flop for storing a single bit. Because the circuits were designed for low speed operation and integrated circuit manufacturing methods were very limited, the gating signals for retrieving data from the memory storage were simple timed signals. For example, with a data latency of 1uS, a circuit designer needed only compute how many clock cycles are necessary to ensure 1uS before strobing read data out of the memory device. This method of latency compensation is both straightforward and easily performed.
Unfortunately, as memory design advances and integrated circuit manufacturing methods improve and diversify, the above noted method becomes more complex. For example, a single memory device manufactured using one or another method may have different data read latencies. Packaging of integrated circuits also may affect data read latencies. Circuit layout and clock frequencies used also affect latencies in some situations. Thus, a present day memory designer determines the maximum data read latency based on a circuit design, layout, manufacturing material, manufacturing process, tolerances in manufacturing, temperature ranges of operation, and so forth. This is a difficult task for the circuit designer, but more importantly the task must be repeated for each potential change or performance degradation results to compensate for a worse possible latency.
In the past, data memory devices relied on a feedback clock from which to generate a data read signal indicative of data availabilityxe2x80x94an end to the data latency period. These feedback clocks compensate for some aspects of the data read latency time relating to data propagation once retrieved. In order to accurately use the feedback clocks, a circuit latency from a data read instruction to data retrieval is calculated and then, a number of clock cycles representative of that length of time or longer is used to provide the remainder of the latency. This overcomes some packaging concerns with changed performance based on changed packaging.
Unfortunately, when designing memory macros for use in ASIC design, it would be advantageous if the macros operated for ASIC manufactured differently and used in varied applications. Prior art circuits either provide reduced performance in order to accommodate a worst case, or they operate only in very limited circumstances.
It would be advantageous to provide a method of determining data read latencies that is closely synchronized with the data read latencies and is somewhat independent of the manufacturing process employed or the environmental conditions of operation.
In accordance with the invention, there is provided a method of indicating data availability comprising the steps of: commencing a data read operation for retrieving data signals based on data stored within a memory storage the data signals having a first propagation delay; providing a strobe signal having a propagation delay similar to the first data propagation delay from the memory device to an external circuit and returning to the memory device; and based on the returned strobe signal indicating data availability, wherein the returned signal, in response to manufacturing and environmental changes, is affected similarly to the retrieved data signals.
In accordance with another aspect of the present invention, there is provided a memory integrated circuit comprising:
a memory storage;
a plurality of data ports;
a circuit for providing data signals of data read from within the memory storage to the plurality of data ports;
a first strobe port;
a circuit for providing a strobe signal to a circuit external the memory integrated circuit via the first strobe port, the strobe signal having similar delays to the provided data signals;
a second strobe port;
a circuit for receiving a returned strobe signal from a circuit external the memory integrated circuit via the second strobe port, the returned signal having a predetermined temporal relation to data availability of data retrieved from the memory storage, wherein in use the returned signal, in response to manufacturing and environmental changes, is affected similarly to the data signals.